/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2018-2019. All rights reserved.
 * Description: Hi309x uboot CPU power management APIs declarations
 * Author: l00416998
 * Create: 2018-05-10
 */
#ifndef __HI309x_PM_H__
#define __HI309x_PM_H__

typedef struct {
    unsigned long reg_base;
    unsigned int reset_addr;
} hi309x_pm_ctrl_mgr;


#define MAX_309x_CORE_NUM (4)
#define A55_CSR_BASE_ADDR 0x14000000
#define A55_CORE0_RVBA_OFFSET 0x10
#define ACTLR_ELX_PWREN (1ul << 7)
#define FCM_PMCTRL_CSR_BASE_ADDR 0x14009000
#define PM_ERR_MSG_LEN  256

/* offset address for FCM_PMCTRL_CSR registers */
#define FCM_PMCTRL_CSR_PMC_FCM_LPMCUCTRL_OFFSET_ADDR 0x0
#define FCM_PMCTRL_CSR_PMC_FCM_WFI_SOURCE_SEL_OFFSET_ADDR 0x4
#define FCM_PMCTRL_CSR_PMC_CORE0_PCTRL_OFFSET_ADDR 0x8
#define FCM_PMCTRL_CSR_PMC_CORE1_PCTRL_OFFSET_ADDR 0xC
#define FCM_PMCTRL_CSR_PMC_CORE2_PCTRL_OFFSET_ADDR 0x10
#define FCM_PMCTRL_CSR_PMC_CORE3_PCTRL_OFFSET_ADDR 0x14
#define FCM_PMCTRL_CSR_PMC_QCTRL_EN_OFFSET_ADDR 0x18
#define FCM_PMCTRL_CSR_PMC_QCTRL_TOUT_OFFSET_ADDR 0x1C
#define FCM_PMCTRL_CSR_PMC_COREX_PCTRL_C01WC_OFFSET_ADDR 0x20
#define FCM_PMCTRL_CSR_PMC_COREX_PCTRL_C23WC_OFFSET_ADDR 0x24
#define FCM_PMCTRL_CSR_PMC_QSTAT_QPEEK_OFFSET_ADDR 0x28
#define FCM_PMCTRL_CSR_PMC_FCM_STANDBY_OFFSET_ADDR 0x2C
#define FCM_PMCTRL_CSR_PMC_CORE0_PSTAT_FEEDBACK_OFFSET_ADDR 0x30
#define FCM_PMCTRL_CSR_PMC_CORE1_PSTAT_FEEDBACK_OFFSET_ADDR 0x34
#define FCM_PMCTRL_CSR_PMC_CORE2_PSTAT_FEEDBACK_OFFSET_ADDR 0x38
#define FCM_PMCTRL_CSR_PMC_CORE3_PSTAT_FEEDBACK_OFFSET_ADDR 0x3C
#define FCM_PMCTRL_CSR_PMC_CORE0_PSTAT_PPEEK_OFFSET_ADDR 0x40
#define FCM_PMCTRL_CSR_PMC_CORE1_PSTAT_PPEEK_OFFSET_ADDR 0x44
#define FCM_PMCTRL_CSR_PMC_CORE2_PSTAT_PPEEK_OFFSET_ADDR 0x48
#define FCM_PMCTRL_CSR_PMC_CORE3_PSTAT_PPEEK_OFFSET_ADDR 0x4C
#define FCM_PMCTRL_CSR_PMC_CORE_DEBUG_INFO0_OFFSET_ADDR 0x50
#define FCM_PMCTRL_CSR_PMC_CORE_DEBUG_INFO1_OFFSET_ADDR 0x54
#define FCM_PMCTRL_CSR_PMC_CORE_PDC_CTRL_OFFSET_ADDR 0x58
#define FCM_PMCTRL_CSR_PMC_CORE_POWER_UP_REQ_OFFSET_ADDR 0x5C
#define FCM_PMCTRL_CSR_PMC_CORE_POWER_DOWN_REQ_OFFSET_ADDR 0x60
#define FCM_PMCTRL_CSR_PMC_CORE_PWRUP_TIME0_OFFSET_ADDR 0x64
#define FCM_PMCTRL_CSR_PMC_CORE_PWRUP_TIME1_OFFSET_ADDR 0x68
#define FCM_PMCTRL_CSR_PMC_CORE_PWRDN_TIME0_OFFSET_ADDR 0x6C
#define FCM_PMCTRL_CSR_PMC_CORE_PWRDN_TIME1_OFFSET_ADDR 0x70
#define FCM_PMCTRL_CSR_PMC_CORE_ISO_TIME0_OFFSET_ADDR 0x74
#define FCM_PMCTRL_CSR_PMC_CORE_ISO_TIME1_OFFSET_ADDR 0x78
#define FCM_PMCTRL_CSR_PMC_CORE_RST_TIME0_OFFSET_ADDR 0x7C
#define FCM_PMCTRL_CSR_PMC_CORE_RST_TIME1_OFFSET_ADDR 0x80
#define FCM_PMCTRL_CSR_PMC_CORE_URST_TIME0_OFFSET_ADDR 0x84
#define FCM_PMCTRL_CSR_PMC_CORE_URST_TIME1_OFFSET_ADDR 0x88
#define FCM_PMCTRL_CSR_PMC_CORE_DBG_TIME0_OFFSET_ADDR 0x8C
#define FCM_PMCTRL_CSR_PMC_CORE_DBG_TIME1_OFFSET_ADDR 0x90
#define FCM_PMCTRL_CSR_PMC_CORE_POWER_STATE_OFFSET_ADDR 0x94
#define FCM_PMCTRL_CSR_PMC_CORE_PWR_DONE_INT_OFFSET_ADDR 0x98

#define FCM_PMCTRL_CSR_PMC_FCM_LPMCUCTRL_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_FCM_LPMCUCTRL_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_FCM_WFI_SOURCE_SEL_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_FCM_WFI_SOURCE_SEL_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE0_PCTRL_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE0_PCTRL_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE1_PCTRL_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE1_PCTRL_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE2_PCTRL_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE2_PCTRL_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE3_PCTRL_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE3_PCTRL_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_QCTRL_EN_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_QCTRL_EN_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_QCTRL_TOUT_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_QCTRL_TOUT_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_COREX_PCTRL_C01WC_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_COREX_PCTRL_C01WC_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_COREX_PCTRL_C23WC_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_COREX_PCTRL_C23WC_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_QSTAT_QPEEK_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_QSTAT_QPEEK_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_FCM_STANDBY_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_FCM_STANDBY_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE0_PSTAT_FEEDBACK_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE0_PSTAT_FEEDBACK_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE1_PSTAT_FEEDBACK_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE1_PSTAT_FEEDBACK_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE2_PSTAT_FEEDBACK_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE2_PSTAT_FEEDBACK_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE3_PSTAT_FEEDBACK_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE3_PSTAT_FEEDBACK_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE0_PSTAT_PPEEK_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE0_PSTAT_PPEEK_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE1_PSTAT_PPEEK_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE1_PSTAT_PPEEK_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE2_PSTAT_PPEEK_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE2_PSTAT_PPEEK_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE3_PSTAT_PPEEK_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE3_PSTAT_PPEEK_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_DEBUG_INFO0_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_DEBUG_INFO0_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_DEBUG_INFO1_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_DEBUG_INFO1_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_PDC_CTRL_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_PDC_CTRL_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_POWER_UP_REQ_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_POWER_UP_REQ_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_POWER_DOWN_REQ_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_POWER_DOWN_REQ_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_PWRUP_TIME0_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_PWRUP_TIME0_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_PWRUP_TIME1_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_PWRUP_TIME1_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_PWRDN_TIME0_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_PWRDN_TIME0_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_PWRDN_TIME1_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_PWRDN_TIME1_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_ISO_TIME0_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_ISO_TIME0_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_ISO_TIME1_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_ISO_TIME1_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_RST_TIME0_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_RST_TIME0_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_RST_TIME1_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_RST_TIME1_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_URST_TIME0_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_URST_TIME0_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_URST_TIME1_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_URST_TIME1_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_DBG_TIME0_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_DBG_TIME0_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_DBG_TIME1_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_DBG_TIME1_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_POWER_STATE_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_POWER_STATE_OFFSET_ADDR)
#define FCM_PMCTRL_CSR_PMC_CORE_PWR_DONE_INT_ADDR \
    (FCM_PMCTRL_CSR_BASE_ADDR + FCM_PMCTRL_CSR_PMC_CORE_PWR_DONE_INT_OFFSET_ADDR)

#endif
